Confluence wiki
Jump to navigation
Jump to search
Description
Confluence is a language for synchronous reactive system design
HDCaml is a hardware design and verification language embedded in Objective Caml. Given a high-level, structural design description, HDCaml will generate a synthesizable Verilog netlist, PSL assertions, and cycle and bit accurate C and SystemC models.
HDCaml circuit simulations can be conducted within Objective Caml and produce VCD waveforms for debugging.