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{{ | {{Wiki | ||
|name=Confluence wiki | |||
|logo=[[Image:HdCamlLogo.png]] | |||
|URL=http://confluent.org/wiki/doku.php | |||
|recentchanges URL=http://confluent.org/wiki/doku.php?do=recent&id= | |||
|wikinode URL=No | |||
|status=Cannot connect | |||
|language=English | |||
|editmode=OpenEdit | |||
|engine=DokuWiki | |||
|maintopic=Software | |||
}} | }} | ||
==Description== | ==Description== | ||
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HDCaml is a hardware design and verification language embedded in Objective Caml. Given a high-level, structural design description, HDCaml will generate a synthesizable Verilog netlist, PSL assertions, and cycle and bit accurate C and SystemC models. | HDCaml is a hardware design and verification language embedded in Objective Caml. Given a high-level, structural design description, HDCaml will generate a synthesizable Verilog netlist, PSL assertions, and cycle and bit accurate C and SystemC models. | ||
see also: http://www.atlassian.com/software/confluence/ | |||
Latest revision as of 22:08, 4 April 2012
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Confluence wiki Recent changes [No WikiNode] [No About] [No Mobile URL] |
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| Status: | Cannot connect |
| Language: | English |
| Edit mode: | OpenEdit |
| Wiki engine: | DokuWiki |
| Wiki license: | [[:Category:Wiki {{{license}}}|{{{license}}}]] |
| Main topic: | Software |
Description[edit]
Confluence is a language for synchronous reactive system design
HDCaml is a hardware design and verification language embedded in Objective Caml. Given a high-level, structural design description, HDCaml will generate a synthesizable Verilog netlist, PSL assertions, and cycle and bit accurate C and SystemC models.