Welcome to WikiIndex — the 'wiki index' of all wikis, wiki people, wiki software, wiki farms, and wiki ideas.
Please add your wiki, and join our community. Note: WikiIndex is not a wiki hosting service.

(please log-in to bypass the anti-spam Captcha and remove this heading notice)

Confluence wiki: Difference between revisions

From WikiIndex
Jump to navigation Jump to search
(New Wiki Template)
(see also)
Line 15: Line 15:


HDCaml is a hardware design and verification language embedded in Objective Caml. Given a high-level, structural design description, HDCaml will generate a synthesizable Verilog netlist, PSL assertions, and cycle and bit accurate C and SystemC models.
HDCaml is a hardware design and verification language embedded in Objective Caml. Given a high-level, structural design description, HDCaml will generate a synthesizable Verilog netlist, PSL assertions, and cycle and bit accurate C and SystemC models.
see also: http://www.atlassian.com/software/confluence/

Revision as of 03:28, 5 May 2006

[{{{URL}}} {{{logo}}}] [{{{URL}}} Confluence wiki]
[{{{recentchanges URL}}} Recent changes]
[No WikiNode]
[No About]
[No Mobile URL]
Founded by:
Status: [[:Category:{{{status}}}|{{{status}}}]]
Language: [[:Category:Wiki {{{language}}}|{{{language}}}]]
Edit mode: [[:Category:{{{editmode}}}|{{{editmode}}}]]
Wiki engine: [[:Category:{{{engine}}}|{{{engine}}}]]
Wiki license: [[:Category:Wiki {{{license}}}|{{{license}}}]]
Main topic: [[:Category:{{{maintopic}}}|{{{maintopic}}}]]

Description

Confluence is a language for synchronous reactive system design

HDCaml is a hardware design and verification language embedded in Objective Caml. Given a high-level, structural design description, HDCaml will generate a synthesizable Verilog netlist, PSL assertions, and cycle and bit accurate C and SystemC models.


see also: http://www.atlassian.com/software/confluence/