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{{ | {{Wiki | | ||
wiki_name | wiki_name = Confluence wiki | ||
wiki_logo = | | wiki_logo = [[Image:HdCamlLogo.png]] | ||
wiki_URL = | | wiki_URL = http://confluent.org/wiki/doku.php | ||
| wiki_recentchanges_URL = http://confluent.org/wiki/doku.php?do=recent&id= | |||
wiki_status = | | wiki_wikinode_URL = No | ||
| wiki_status = Active | |||
wiki_language = | | wiki_language = English | ||
wiki_editmode = | | wiki_editmode = OpenEdit | ||
wiki_engine = | | wiki_engine = DokuWiki | ||
wiki_maintopic = | | wiki_maintopic = Software | ||
}} | }} | ||
==Description== | ==Description== | ||
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HDCaml is a hardware design and verification language embedded in Objective Caml. Given a high-level, structural design description, HDCaml will generate a synthesizable Verilog netlist, PSL assertions, and cycle and bit accurate C and SystemC models. | HDCaml is a hardware design and verification language embedded in Objective Caml. Given a high-level, structural design description, HDCaml will generate a synthesizable Verilog netlist, PSL assertions, and cycle and bit accurate C and SystemC models. | ||
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