Confluence wiki: Difference between revisions

420 bytes removed ,  6 March 2006
New Wiki Template
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(New Wiki Template)
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{{Wiki_List |
{{Wiki |
wiki_name =               Confluence wiki                                         |
  wiki_name             = Confluence wiki
wiki_logo =                 [[Image:HdCamlLogo.png]]                                   |
| wiki_logo             = [[Image:HdCamlLogo.png]]
wiki_URL =                 http://confluent.org/wiki/doku.php                                                               |
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wiki_lastreviewed  =        16-Jan-06                  |
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wiki_language =             English                   |
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wiki_editmode =             OpenEdit             |
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wiki_maintopic =           Software
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==Description==
==Description==
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HDCaml is a hardware design and verification language embedded in Objective Caml. Given a high-level, structural design description, HDCaml will generate a synthesizable Verilog netlist, PSL assertions, and cycle and bit accurate C and SystemC models.
HDCaml is a hardware design and verification language embedded in Objective Caml. Given a high-level, structural design description, HDCaml will generate a synthesizable Verilog netlist, PSL assertions, and cycle and bit accurate C and SystemC models.
HDCaml circuit simulations can be conducted within Objective Caml and produce VCD waveforms for debugging.
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