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==Description== | ==Description== | ||
Confluence is a language for synchronous reactive system design | Confluence is a language for synchronous reactive system design | ||
HDCaml is a hardware design and verification language embedded in Objective Caml. Given a high-level, structural design description, HDCaml will generate a synthesizable Verilog netlist, PSL assertions, and cycle and bit accurate C and SystemC models. | |||
HDCaml circuit simulations can be conducted within Objective Caml and produce VCD waveforms for debugging. | |||
Revision as of 21:25, 8 February 2006
Description
Confluence is a language for synchronous reactive system design
HDCaml is a hardware design and verification language embedded in Objective Caml. Given a high-level, structural design description, HDCaml will generate a synthesizable Verilog netlist, PSL assertions, and cycle and bit accurate C and SystemC models.
HDCaml circuit simulations can be conducted within Objective Caml and produce VCD waveforms for debugging.