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	HDCaml is a hardware design and verification language embedded in Objective Caml. Given a high-level, structural design description, HDCaml will generate a synthesizable Verilog netlist, PSL assertions, and cycle and bit accurate C and SystemC models.		HDCaml is a hardware design and verification language embedded in Objective Caml. Given a high-level, structural design description, HDCaml will generate a synthesizable Verilog netlist, PSL assertions, and cycle and bit accurate C and SystemC models.


			see also: http://www.atlassian.com/software/confluence/