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{{Wiki_List | | {{Wiki_List | | ||
wiki_name = Confluence wiki | | wiki_name = Confluence wiki | | ||
wiki_logo = [[Image: | wiki_logo = [[Image:HdCamlLogo.png]] | | ||
wiki_URL = http://confluent.org/wiki/doku.php | | wiki_URL = http://confluent.org/wiki/doku.php | | ||
wiki_recentchanges = http://confluent.org/wiki/doku.php?do=recent&id= | | wiki_recentchanges = http://confluent.org/wiki/doku.php?do=recent&id= | | ||
Revision as of 21:27, 8 February 2006
Description
Confluence is a language for synchronous reactive system design
HDCaml is a hardware design and verification language embedded in Objective Caml. Given a high-level, structural design description, HDCaml will generate a synthesizable Verilog netlist, PSL assertions, and cycle and bit accurate C and SystemC models.
HDCaml circuit simulations can be conducted within Objective Caml and produce VCD waveforms for debugging.