Confluence wiki
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| Status: | Cannot connect |
| Language: | English |
| Edit mode: | OpenEdit |
| Wiki engine: | DokuWiki |
| Wiki license: | [[:Category:Wiki {{{license}}}|{{{license}}}]] |
| Main topic: | Software |
Description[edit]
Confluence is a language for synchronous reactive system design
HDCaml is a hardware design and verification language embedded in Objective Caml. Given a high-level, structural design description, HDCaml will generate a synthesizable Verilog netlist, PSL assertions, and cycle and bit accurate C and SystemC models.
